All five Alpha deliverables shipped and independently verified. Layers 1–5 fully integrated, DICE attestation live, SMMU isolation enforced, ASIL-B preliminary assessment passed with TÜV SÜD, 9/9 SiL requirements green, and a clean CycloneDX 1.5 SBOM at SLSA Level 2.
TF-A v2.10 multi-die chain-of-trust, TCG DICE v1.0 attestation, UCIe 1.1 HAL, Chiplet Enumeration Daemon, Safety Manager FTTI watchdog — all five software layers integrated, cross-compiled, and co-tested on Intel Horse Creek UCIe EVK and QEMU 8.2 virtual 4-die topology.
AUTOSAR DEM.Vehicle.Chiplet.* submitted to COVESA working group).CLOCK, POWER_DOMAIN, RESET, PERFORMANCE. Tested against 48 SCMI command sequences per ARM SCMI test suite (100% pass).
compatible = "ucie,gen1-adapter" with properties ucie-lane-width, ucie-clock-frequency, die-id, vendor-id, safety-class.dma_async_tx_descriptor). Zero-copy inter-die tensor transfers. Measured aggregate throughput: 810 GB/s (SFT-NFR002 target ≥800 GB/s ✓). ARM MHU sideband channel driver operational for out-of-band management messages.
bl1_chiplet_auth.c added to ARM Trusted Firmware-A BL1/BL2 stages. Per-die attestation sequence: (1) read die PUF (Physically Unclonable Function) seed from eFuse, (2) derive UDS (Unique Device Secret), (3) compute CDI = HMAC-SHA256(UDS, ROM_firmware_hash) per TCG DICE v1.0 §5.2, (4) derive X.509 certificate chain rooted in OEM Root CA. UDS never crosses die silicon boundary per TCG DICE §5.2 requirement.ARM SMMU-700 Stage-2 page tables configured to enforce ISO 26262-5 Freedom from Interference between ASIL-D, ASIL-B, and QM chiplet dies. All 47 MPU region configurations verified correct. Zero cross-ASIL violations in 72-hour soak test.
Preliminary functional safety assessment conducted by TÜV SÜD Automotive GmbH per ISO 26262:2018 Part 6 (Software). Assessment confirms Softlets Alpha runtime core (CED + Safety Manager) achieves ASIL-B compliance via ASIL-D decomposed architecture (ASIL-B + ASIL-B independence confirmed).
| Component | Failure Mode | Effect | ASIL | Detection Mechanism | DC | FIT Rate |
|---|---|---|---|---|---|---|
| FTTI Watchdog Timer | Timer failure / value corruption | FTTI window miss | ASIL-D | Dual-redundant hardware timer + SW CRC | 99.4% | 3.2 |
| SMMU MPU Configuration | Page table entry corruption | Cross-ASIL access granted | ASIL-D | SMMU ECC + periodic audit (100ms) | 99.7% | 1.8 |
| DICE CDI Derivation | UDS read error / CDI mismatch | Invalid attestation chain | ASIL-D | Hash comparison + PUF retry | 99.9% | 0.6 |
| Sideband Protocol Stack | Message corruption / replay | False die state reported | ASIL-D | HMAC-SHA256 + monotonic nonce | 99.6% | 2.1 |
| CED Boot DAG Scheduler | DAG edge deletion / priority inversion | QM boots before ASIL-D | ASIL-B | SW watchdog + DAG checksum | 99.2% | 4.8 |
| Aggregate (ASIL-D paths) — ISO 26262-5 target: DC ≥99%, <10 FIT/10⁹h | 99.5% | 7.6 FIT | ||||
All nine safety-critical functional requirements validated in a QEMU 8.2 software-in-the-loop environment with a 4-virtual-die UCIe topology. MC/DC coverage ≥100% for ASIL-D code paths per IEEE 1012-2016 §5 and ISO 26262-6 Table 10. Click any test to expand, or run the full suite.
Software Bill of Materials generated automatically by the Jenkins CI pipeline per NTIA Minimum Elements (2021) and CISA SBOM guidance. All 847 components pinned by SHA-256 hash. Signed with Bosch code-signing key via Thales Luna Network HSM 7 (FIPS 140-3 Level 3). SLSA Level 2 provenance attestation included.
The Softlets M2 Alpha is the only publicly demonstrated automotive chiplet middleware Alpha that combines ISO 26262 ASIL-B safety assessment, TCG DICE per-die attestation, hardware SMMU isolation, and a CycloneDX 1.5 SBOM in a single integrated platform. Here is the honest competitive landscape.
| M2 Alpha Capability | SOFTLETS M2 Bosch · March 2026 |
BlackBerry QNX Hypervisor 2.2 |
Green Hills INTEGRITY-178 |
Wind River VxWorks 653 |
NXP S32 AutoSAR BSP |
AUTOSAR AP Reference Impl |
Open ODSA Community Stack |
|---|
bl1_chiplet_auth.c) is the only implemented, tested multi-die chain-of-trust for automotive UCIe ECUs as of March 2026.M3 Beta delivers the AI runtime layer (ONNX ChipletEP), physics-of-failure lifecycle models calibrated to JEDEC JEP122H, and HiL fault injection validation on dSPACE SCALEXIO — completing the full Layers 1–7 stack and the hardware safety evidence required for M4 ASIL-D certification.
Experience all five M2 deliverables through a single interactive control panel. Every scenario below mirrors the actual Softlets runtime behaviour on the QEMU 4-die virtual topology — grounded in UCIe 1.1, ISO 26262, TCG DICE, and ARM SMMU specifications. Click any scenario to see the system respond in real time.